Describe typical applications for Binary ripple counter using jk flip flop Type flip-flops. Recognize standard circuit symbols for D Type flip-flops. Recognize D Type flip-flop integrated circuits. Recognise alternative forms of D Type flip-flops.
Construct timing diagrams to explain the operation of D Type flip-flops. Use software to simulate D Type flip-flops. 2 is overcome by the D type flip-flop. As long as the clock input is low, changes at the D input make no difference to the outputs.
The basic D Type flip-flop shown in Fig. 1 is called a level triggered D Type flip-flop because whether the D input is active or not depends on the logic level of the clock input. 1, then S must be 1 and R must be 0, therefore Q is SET to 1. 0 then R must be 1 and S must be 0, causing Q to be reset to 0. As can be seen from the timing diagram shown in Fig 5. 2, if the data at D changes during this time, the Q output assumes the same logic level as the D.
The Edge Triggered D Type Flip-flop Fortunately ripple though can be largely prevented by using the Edge Triggered D Type flip-flop illustrated in Fig 5. Synchronous and Asynchronous Inputs A further refinement in Fig. The SET and RESET inputs in Fig 5. The flip-flop is positive edge triggered, which is shown on the CK input in Fig 5. Edge triggered D type flip-flop with asynchronous preset and clear capability’, although developed from the basic SR flip-flop becomes a very versatile flip-flop with many uses.
A timing diagram illustrating the action of a positive edge triggered device is shown in Fig. At the positive going edges of clock pulses a and b, the D input is high so Q is also high. Just before pulse c the D input goes low, so at the positive going edge of pulse c, Q goes low. D has also returned to its high state before pulse e, Q remains high during pulse e. D and immediately making Q high.
D is still high at the positive going edge of pulse f, and because the flip-flop is positive edge triggered, the change in the logic level of D during pulse f is ignored until the positive going edge of pulse g, which resets Q to its low level. At the positive going edge of pulse j, input D regains control, but as D is high and Q is already high, no change in output Q occurs. At the positive going edge of a CK pulse, Q will assume the same level as input D, unless either asynchronous input has control. The action of the asynchronous inputs overrides any effect of the D input.
The D Type Master Slave Flip-Flop Yet a further version of the D Type flip-flop is shown in Fig. 6 where two D type flip-flops are incorporated in a single device, this is the D type master-slave flip-flop. Circuit symbols for the master-slave device are very similar to those for edgetriggered flip-flops, but are now divided into two sections by a dotted line, as also illustrated in Fig 5. Notice that although the clock inputs on the circuit symbols suggest that this is a negative edge triggered device, data is actually taken into FF1 on the POSITIVE going edge of the CK pulse. After the positive going edge of the external CK pulse, FF1 ignores any further data at D, and at the negative going edge of the external CK pulse, the data being held at q1 is taken into the d2 input of FF2 which now sees a positive going edge of the inverted CK pulse. Q output does look rather like a negative edge triggered device, as any change in the output occurs at the falling edge of the clock pulse. 7 this is not really negative edge triggering, because the data appearing at Q as the clock pulse returns to logic 0, is actually the data that was present at input D at the RISING edge of the CK pulse.
Toggle flip-flops are the basic components of digital counters, and all of the D type devices are adaptable for such use. When an electronic counter is used for counting, what are actually being counted are pulses appearing at the CK input, which may be either regular pulses derived from an internal clock, or they can be irregular pulses generated by some external event. Most edge-triggered flip-flops can be used as toggle flip-flops including the D type, which can be converted to a toggle flip-flop with a simple modification. D input as shown in Fig.
The actual input is now CK. The effect of this mode of operation is also shown in the timing diagram in Fig. 8 using a positive edge triggered D type flip-flop. This logic 0 is now fed back to D, but it is important that it is not immediately accepted into the D input, otherwise oscillation could occur with D continually changing between 1 and 0.